The invention relates generally to semiconductor packaging and, in particular, to systems and methods for joining a chip to a substrate.
A die or chip includes integrated circuits formed by front-end-of-line processing using the semiconductor material of a wafer, a local interconnect level formed by middle-end-of-line processing, and stacked metallization levels of an interconnect structure formed by back-end-of line processing. After the wafer is diced, each chip may be joined with a substrate using a controlled collapse chip connection or flip chip process. In a flip chip process, reflowed solder bumps provide mechanical and electrical connections between pads in the top metallization level of the chip and a complementary set of pads on the substrate. The solder bumps can be formed on the pads of the chip using any number of techniques, including electroplating, evaporation, printing, and direct placement. Reflow of the solder bumps establishes solder joints physically and electrically connecting the pads on the chip with the complementary set of pads on the substrate.
Systems and methods for joining a chip to a substrate are needed that improve on existing joining systems and methods.